Semiconductor companies face a constant faster-better-cheaper battle with their competitors. You do 2GHz, they do 2.1GHz, you do 10nm, they do 7nm. Customers understand this as well as the vendors, so the whole market marches in lockstep together.
This is the story of when different factors crept in to the decision process and hurt one company for many years.
In the Early Days of FPGAs
FPGAs (field-programmable gate arrays, a type of chip which can be programmed so you can get to market faster) are well established now, but in the mid 1980s Actel and Xilinx were the first two vendors. Actel’s anti-fuse technology was a bit faster and a bit cheaper than Xilinx’s reprogrammable SRAM technology. It was also a lot smaller, because to use a Xilinx SRAM part required a second chip on the board to program it on power up. Actels parts were faster, cheaper and consumed less space, so Actel should have kicked ass, right?
How Actel Saw It
On the other hand, the Xilinx chips were reprogrammable, either during the design phase for prototyping, or even in-circuit, so you could reprogram the hardware logic while it was operating. Actel knew that the vast majority of customer designs did not require Xilinx’s reprogrammability. In fact, Actel’s quantitative user surveys clearly showed that fewer than 10% of designs required in-circuit reprogrammability.
So why was Xilinx beating them in deal after deal, with parts that were more expensive, slower and larger board footprint?
The Customer Saw Things Differently
Eventually they figured out what was happening. When each new chip family was launched, Actel and Xilinx would give every customer a sample. The problem was, the Actel sample could be used exactly once as a test, while the Xilinx sample could be reused as a prototyping platform forever. You could reprogram it 5 times today, and 5 times tomorrow, and hundreds of times if necessary to get your design right. This meant that by prototyping on the Xilinx part, the engineering team could get their project done faster, at lower risk and at lower cost.
With Actel, to respin a design 5 times a day would cost 5 chips a day, and those were $2K or $4K parts. Junior engineers weren’t going to burn through 5 chips in a day if they cost $4K each. The VP of Engineering didn’t want to see $4K parts in the trash can every day!
How the CFO Saw Things
In the end, the VP of engineering didn’t care if the production part cost 10% more, because Xilinx helped the company get to market faster. Xilinx promoted in-system reprogrammability to get attention, but in reality, it was this reduced prototyping cost that won the deal. Actel assumed faster-cheaper-smaller would win the day, but improved time to market ended up as Xilinx’s trump card.